1. Field of the Invention
The present invention relates to a technique of an interrupt control apparatus, an interrupt control system, an interrupt control method, and an interrupt control program.
2. Description of the Related Art
In some computing systems, hardware of auxiliary type is used for improving a processing capacity of a specific function. Such hardware can substitute for a CPU (Central Processing Unit) in performing a processing for a specific function. Use of the hardware allows the CPU to concentrate its computing resource on other function. Additionally, the hardware is well optimized so as to realize such a specific function. Thus, performance of an overall computing system can be improved. This results in reducing load of an application running on an OS (Operating System) executed by the CPU. Such hardware is generally called an accelerator.
Some accelerators focus on a communication processing. Such an accelerator for communication processing (which may be simply referred to as an accelerator hereinafter) executes a given protocol processing within hardware of its own. Another accelerator for communication processing for use in controlling has a function of transmitting and receiving a communication packet in a prescribed constant period.
The accelerator for communication processing performs a processing coordinating with a CPU and thus has a function of notifying the CPU of an interrupt if a prescribed event occurs. Such an event includes a protocol processing completion, a packet transmission completion, a packet receipt completion, and an occurrence of a failure (for example, a receipt of an abnormal packet).
Upon notification of an interrupt, the CPU obtains necessary information from the accelerator for communication processing and executes a prescribed processing. The CPU may set prescribed information at the accelerator for communication processing. Such a prescribed processing includes a received packet acquisition, a transmitting packet setting, an instruction value setting, and an acquisition of a communication processing result. The processing is executed as an interrupt handler in an OS. In some cases, an interrupt handler runs a specific application. In other cases, after a minimum required processing is carried out in an interrupt handler, the interrupt handler makes another interrupt handler start with a delay.
If a computer having an accelerator for communication processing concurrently controls a plurality of controlled objects, a period for the control is a period of a controlled object having the shortest control period among the plurality of controlled objects or a period corresponding to the largest common factor of control periods of the plurality of controlled objects. A system with a plurality of controlled objects thus has a tendency to have a shorter communication period and a faster transmission and receipt of a communication.
Herein, a problem occurs in transmitting and receiving a control packet in a fast period such as a motion control or a servomotor control, using an accelerator for communication processing. If a communication period of a communication packet is faster compared with performance of a CPU on which an OS operates, interrupts on the OS occur frequently, which prevents the OS from performing a processing other than the interrupt control processing.
Published Japanese translation of PCT international publication for patent application, Publication No. 2003-524312 (to be referred to as JP 2003-524312A hereinafter) discloses a method and an apparatus of presenting an interrupt in a network interface in which an interrupt is generated in response to a transfer of a packet only if a prescribed period of time has elapsed or a prescribed number of packets have been transferred since a previous interrupt was processed. According to a technique described in JP 2003-524312A, generation of an interrupt handler can be prevented, and overhead cost of communications can be reduced in a general-purpose communication processing in which priority is given to a throughput.
Japanese Laid-Open Patent Application, Publication No. 2006-163730 (to be referred to as JP 2006-163730A hereinafter) discloses an interrupt control method of suspending an interrupt processing, and a controller using the method if a prescribed processing time has elapsed in a prescribed period. According to a technique of JP 2006-163730A, running time of an application is ensured.
However, the technique described in JP 2003-524312A is not applied to a communication in a fast period which is accompanied by a control or other operation. Therefore, the technique of JP 2003-524312A may result in preventing generation of a packet regarding a control computing having a time constraint. If a control computing is executed after a prescribed period of time has elapsed or after a prescribed number of packets are transmitted or received, performance of controlling is decreased without meeting the time constraint. That is, in the technique of JP 2003-524312A, an interrupt is blocked from when a previous interrupt was generated until when a prescribed time has elapsed or a prescribed number of packets have been transferred. If a processing has a time constraint, a time required for the processing may have elapsed before the above-mentioned period of time for blocking an interrupt terminates.
According to the technique described in JP 2006-163730A, a processing of a packet regarding a control computing having a time constraint is delayed, and performance of controlling is decreased. That is, if a communication control is required to be performed within a short period of time, there is a possibility that the above-mentioned period of preventing an interrupt delays the entire processing.
The present invention has been made in light of the background and in an attempt to realize an efficient interrupt in a communication in a fast period requiring an interrupt.